1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly to a memory apparatus that has a training function and a memory system using the same.
2. Related Art
A synchronous memory apparatus has an interface that is synchronized with a system bus. To put it another way, when an external device transmits a data signal to the synchronous memory apparatus, or when the synchronous memory apparatus transmits a data signal to an external device, the transmission of the data signal is synchronized with a clock. For example, the transmission of the data signal may be synchronized with a strobe signal which has the same cycle as a clock. During read and write operations of the memory apparatus, data input/output may be synchronized with the strobe signal. When the memory apparatus performs write and read operations at high speeds, it is important to control timings with respect to a clock, a strobe signal, and a data signal. As the write and read operation speed of a memory apparatus increases, however, timing skew may occur.
In order to cope with this problem, a memory apparatus may perform operations such as write training and write leveling. There are various ways to realize the write training and the write leveling. For example, the write training may be an operation that delays a strobe signal to secure a data latch margin, and the write leveling may be an operation that controls the skew between the clock and the strobe signal.